Andrew Boutros

Peer-reviewed Articles

* indicates equal contribution

Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs [PDF]

Eriko Nurvitadhi, Andrew Boutros, Prerna Budhkar, Ali Jafari, Dongup Kwon, David Sheffield, Abirami Prabhakaran, Karthik Gururaj, Pranavi Appana and Mishali Naik
International Conference on Field-Programmable Technology (FPT), December 2019, Tianjin, China

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs [PDF]

Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory Chen, Phil Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr and Aravind Dasu
International Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2019, San Diego, USA (Acceptance Rate: 26%)

Math Doesn’t Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs [PDF]

Andrew Boutros*, Mohamed Eldafrawy*, Sadegh Yazdanshenas, and Vaughn Betz
International Symposium on Field-Programmable Gate Arrays (FPGA), February 2019, Monterey, USA (Acceptance Rate: 19%)

Evaluating and Enhancing Intel Stratix 10 FPGAs for Persistent Real-Time Artificial Intelligence [Poster]

Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory Chen, Phil Knag, Raghavan Kumar, Ram Krishnamurthy, and Debbie Marr
International Symposium on Field-Programmable Gate Arrays (FPGA), February 2019, Monterey, USA

You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference [PDF]

Andrew Boutros, Sadegh Yazdanshenas, and Vaughn Betz
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol. 11, December 2018

Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs [PDF]

Andrew Boutros, Sadegh Yazdanshenas, and Vaughn Betz
International conference on Field-Programmable Logic and Applications (FPL), August 2018, Dublin, Ireland (Acceptance Rate: 17%)
S. Vassiliadis Best Paper Award

Build Fast, Trade Fast: FPGA-based High-Frequency Trading using High-Level Synthesis [PDF]

Andrew Boutros*, Brett Grady*, Mustafa Abbas*, and P. Chow
International conference on Reconfigurable Computing and FPGAs (ReConFig), December 2017, Cancun, Mexico

Hardware Acceleration of Novel Chaos-Based Image Encryption for IoT Applications [PDF]

Andrew Boutros, Salma Hesham, Barbara Georgey, and Mohamed Abd El Ghany
International conference on Microelectronics (ICM), December 2017, Beirut, Lebanon

A HW/SW Co-Design of the HOG Algorithm on Xilinx Zynq SoC [PDF]

Jens Rettkowski*, Andrew Boutros*, and Diana Goehringer
Journal of Parallel and Distributed Computing (JPDC), Vol. 109, November 2017

Real-time Pedestrian Detection on a Xilinx Zynq using the HOG Algorithm [PDF]

Jens Rettkowski*, Andrew Boutros*, and Diana Goehringer
International conference on Reconfigurable Computing and FPGAs (ReConFig), December 2015, Cancun, Mexico
Best Paper Award

Dissertations

Enhancing FPGA Architecture for Efficient Deep Learning Inference [PDF]

MASc Thesis, University of Toronto, August 2018
Advisor: Prof. Vaughn Betz

Pedestrian Detection based on the HOG Algorithm on a Xilinx Zynq FPGA [PDF]

BSc Thesis, German University in Cairo, July 2015
Advisor: Prof. Diana Goehringer (Ruhr University Bochum)